1. Field of the Invention
The present invention relates to an inspecting method, an inspecting apparatus, and a defect correction method, all for an active matrix substrate which constitutes a display apparatus in conjunction with a display medium such as liquid crystal.
2. Description of the Related Art
In an active matrix method, pixel electrodes are disposed in a matrix form on an insulating substrate, and the respective pixel electrodes are independently driven. The active matrix method is practically used for a display apparatus such as a liquid crystal television, a word processor display, or a terminal display apparatus in a computer. As a switching element for driving each pixel electrode, a thin film transistor (TFT) device, a metal-insulator-metal (MIM) device, an MOS transistor device, a diode, a varistor, and the like are generally known.
FIG. 29 is a schematic circuit diagram of an active matrix substrate utilizing a TFT as a switching element. FIG. 30 is a partially enlarged view of the active matrix substrate shown in FIG. 29. An active matrix display apparatus is constructed of the active matrix substrate, a counter substrate disposed so as to face the active matrix substrate, and a liquid crystal layer interposed between the active matrix substrate and the counter substrate. On an insulating substrate of the active matrix substrate, a plurality of gate bus lines 1 as scanning lines are disposed in parallel. A plurality of source bus lines 2 as signal lines are disposed in parallel so as to cross the gate bus lines 1. In the vicinity of each of the crossings of the gate bus lines 1 and the source bus lines 2, a TFT 3 is disposed. The TFT 3 is connected to a pixel electrode 4 which is provided in a rectangular area defined by the adjoining gate bus lines 1 and source bus lines 2.
On a face of the counter substrate which faces the active matrix substrate and is in contact with the liquid crystal layer, counter electrodes 5 are formed. Between a counter electrode 5 and the corresponding pixel electrode 4, a pixel capacitance C.sub.LC is formed.
An auxiliary capacitance (C.sub.S) 6 is provided in parallel with the pixel capacitance C.sub.LC. One of the electrodes of the auxiliary capacitance 6 is connected to the pixel electrode 4. The other electrode thereof is connected to a gate bus line 1 to which a pixel electrode 4 which is adjacent to the pixel electrode 4 connected to the former electrode is connected via a TFT 3. That is, the above-described active matrix substrate has a so-called Cs-On-Gate structure.
In a conventional inspecting method for detecting a defect in the active matrix substrate having the Cs-On-Gate structure, signals A1, A2, B, and C shown in FIG. 31 are used. The signal A1 is supplied to odd-numbered gate bus lines 1 via line 7 shown in FIG. 29. The signal A2 is supplied to even numbered gate bus lines 1 via line 8 shown in FIG. 29. These signals A1 and A2 control the ON/OFF states of the TFTs 3 by changing voltages applied to the gate electrodes of the TFTs 3 which are connected to the respective pixel electrodes 4. The signal B is supplied to the source bus lines 2 via line 9, and written into the respective pixel electrodes 4 by the TFTs 3. The voltage level of the signal B is maintained after it is written in the respective pixel electrodes 4 until a new signal is written in the next frame. The signal C is supplied to the counter electrodes 5 on the counter substrate, and it is fixed to an optimum voltage level.
FIG. 32 is a schematic circuit diagram showing an active matrix substrate having a construction different from that of FIG. 29. FIG. 33 is a partially enlarged view of the active matrix substrate. The active matrix substrate is disposed so as to face a counter substrate, the same as the active matrix substrate shown in FIG. 29. An active matrix display apparatus is constructed of the active matrix substrate, the counter substrate, and a liquid crystal layer which is interposed between these substrates. On an insulating substrate of the active matrix substrate, a plurality of gate bus lines 1 as scanning lines are disposed in parallel. A plurality of source bus lines 2 as signal lines are disposed in parallel so as to cross the gate bus lines 1. In the vicinity of each of the crossings of the gate bus lines 1 and the source bus lines 2, a TFT 3 is disposed. The TFT 3 is connected to a pixel electrode 4 which is provided in a rectangular area defined by the adjoining gate bus lines 1 and source bus lines 2.
On a face of the counter substrate which faces the active matrix substrate and is in contact with the liquid crystal layer, counter electrodes 5 are formed. Between a counter electrode 5 and the corresponding pixel electrode 4, a pixel capacitance C.sub.LC is generated.
An auxiliary capacitance (C.sub.S) 6 is provided in parallel with the pixel capacitance C.sub.LC. One of the electrodes of the auxiliary capacitance 6 is connected to the pixel electrode 4. The other electrode thereof is connected to an auxiliary capacitance common line 29. That is, the above-described active matrix substrate shown in FIG. 32 has a so-called Cs-On-Common structure.
In a conventional inspecting method for detecting a defect in the active matrix substrate having the Cs-On-Common structure, signals A3, B, and C shown in FIG. 34 are used. The signal A3 is supplied to gate bus lines 1 via line 28 shown in FIG. 32. The signal A3 controls the ON/OFF states of the TFTs 3 by changing voltages applied to the gate electrodes of the TFTs 3 which are connected to the respective pixel electrodes 4. The signal B is supplied to the source bus lines 2 via line 9. The voltage level of the signal B is maintained after the signal B is written into the respective pixel electrodes 4 until a new signal is written in the next frame. The signal C is supplied to the counter electrodes 5 on the counter substrate, and it is fixed to an optimum voltage level.
However, according to the above-mentioned conventional inspecting methods, even if there occur some defects in the active matrix substrate having the Cs-On-Gate structure shown in FIG. 29 or in the active matrix substrate having the Cs-On-Common structure shown in FIG. 32, some of the defects cannot be detected. Even in a case where the defects can be detected, the types of the defects cannot be specified.
For example, according to the conventional inspecting methods, a defect due to ON failure, i.e., the poor ON characteristics of a TFT 3 can be detected based on the shape of the rising edge d of the waveform D indicative of the potential of the drain electrode when an inspecting signal is supplied to the source bus line 2. The waveform D indicative of the potential of the drain electrode and the rising edge d are shown by broken lines in FIGS. 31 and 34. FIG. 31 shows the case of the active matrix substrate having the Cs-On-Gate structure. FIG. 34 shows the case of the active matrix substrate having the Cs-On-Common structure.
However, as described above, the voltage level of the signal B is maintained after the signal B is written into respective pixels by the TFTs 3 until a new signal is written thereinto in the next frame. This means that the voltage level of the signal B is maintained even when the OFF characteristics of a TFT 3 are deteriorated due to a leakage between the source electrode and the drain electrode of the TFT 3. Accordingly, a defect due to OFF failure of the TFT 3 cannot be detected. Also in a case where a leakage occurs in another portion, for example, between the pixel electrode 4 and the source bus line 2 or the like, a defect due to leakage cannot be detected for the above-mentioned reasons.
As described above, the voltage level of the signal C supplied to the counter electrodes 5 is fixed to the optimum counter voltage level. Accordingly, a defect due to leakage caused by metallic dust or the like between the counter electrode 5 and the pixel electrode 4 and a defect due to leakage caused by insulation failure between a pair of electrodes of the auxiliary capacitance 6 can be detected. However, the above defects cannot be distinguished from a defect due to OFF failure caused by an insulation failure between the source electrode and the drain electrode of the TFT 3.
As described above, according to the conventional inspecting methods, a defect due to OFF failure caused by a leakage between the source electrode and the drain electrode of the TFT 3, and defects due to leakage caused between the pixel electrode 4 and the source bus line 2, between the counter electrode 5 and the pixel electrode 4, and between the electrodes of the auxiliary capacitance 6 could not be detected. In a case where defects on the active matrix substrate could be detected, a defect due to OFF failure could not be distinguished from a defect due to leakage. Furthermore, portions of the detected defects could not be specified on the active matrix substrate, so that the defects could not be substantially corrected. This results in a problem in the reduction of yield.